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NCP5395T 2/3/4-Phase Controller with On Board Gate Drivers for CPU Applications
The NCP5395T provides up to a four-phase buck solution which combines differential voltage sensing, differential phase current sensing, and adaptive voltage positioning to provide accurately regulated power for both Intel and AMD processors. It also receives power saving command (PSI) from CPU, and operates in a single phase emulation diode mode to obtain a high efficiency at light load. Dual-edge pulse-width modulation (PWM) combined with precise inductor current sensing provides the fastest initial response to dynamic load events both in power saving and normal modes. Dual-edge multiphase modulation reduces the total bulk and ceramic output capacitance required therefore reducing the system cost to meet transient regulation specifications. The on board gate drivers includes adaptive non overlap and power saving operation. A high performance operational error amplifier is provided to simplify compensation of the system. Patented Dynamic Reference Injection further simplifies loop compensation by eliminating the need to compromise between closed-loop transient response and Dynamic VID performance.
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QFN48, 7x7 CASE 485AJ 1 48
MARKING DIAGRAM
48 1
NCP5395T AWLYYWWG
* * * * * * * * * * * * * * * * * * * * * * *
Meets Intel's VR11.1 and AMD's 6 Bit Code Specifications Enhanced Power Saving Function * Internal Soft Start Dual-edge PWM for Fastest Initial Response to Transient Loading High Performance Operational Error Amplifier Dynamic Reference Injection (Patent #US07057381) DAC Range from 0.5 V to 1.6 V DAC Feed Forward Function (Patient Pending) 0.5% DAC Voltage Accuracy from 1.0 V to 1.6 V True Differential Remote Voltage Sensing Amplifier Phase-to-Phase Current Balancing "Lossless" Differential Inductor Current Sensing Accurate Current Monitoring (IMON) Differential Current Sense Amplifiers for Each Phase Adaptive Voltage Positioning (AVP) Oscillator Frequency Range of 125 kHz - 1 MHz Latched Over Voltage Protection (OVP) Guaranteed Startup into Pre-Charged Loads Threshold Sensitive Enable Pin for VTT Sensing Power Good Output with Internal Delays Output Disable Control Turn Off of Both Phase Pair MOSFETs Thermally Compensated Current Monitoring Adaptive-Non-Overlap Gate Drive Circuit Thermal Shutdown Protection * This is a Pb-Free Device
A WL YY WW G
= Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package VBST3 TG3 SWN3 DRVON BST2 TG2 SWN2 BG2 VCCP SWN1 TG1 BST1 AGND Down-bonded to Exposed Flag BG1 G4 VRRDY EN CS1N CS1P CS2N CS2P CS3N CS3P CS4N CS4P IMON VSP VSN DIFFOUT COMP VFB VDRP VDFB CSSUM DAC 12VMON VCC Package QFN48 (Pb-Free) Shipping 2500/Tape & Reel Publication Order Number: NCP5395T/D
48 1 BG3 PSI VID0 VID1 VID2 VID3 VID4 VID5 VID6 VID7/AMD ROSC ILIM
ORDERING INFORMATION
Device NCP5395TMNR2G
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
Applications
* Desktop Processors
(c) Semiconductor Components Industries, LLC, 2009
June, 2009 - Rev. 0
1
NCP5395T
VID0 VID1 VID2 VID3 VID4 VID5 VID6 VID7/AMD
PSI DAC
Flexible DAC Overvoltage Protection VCCP
+
BST1 + Phase 1 Gate Driver with Adaptive Non-overlap TG1 SWN1 BG1
VSN VSP
+ Diff Amp
-
DIFFOUT 1.3 V Error Amp VFB + + COMP VDRP VDFB CSSUM CS1P CS1N CS2P CS2N CS3P CS3N CS4P CS4N + + + -2/3 + + Gain = 6 + Gain = 6 + Gain = 6 + Gain = 6 IMON DRVON + Control, Fault Logic and Monitor Circuits + + Phase 3 Gate Driver with Adaptive Non-overlap BST3 TG3 SWN3 BG3 G4 Phase 2 Gate Driver with Adaptive Non-overlap BST2 TG2 SWN2 BG2
+ + -
Oscillator ROSC
ILIM EN VCC 4.25 V
ILimit
12VMON
+ -
VR_RDY UVLO
GND (FLAG)
Figure 1. NCP5395T Functional Block Diagram
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NCP5395T
VTT
PSI#_CPU VID0 VID1 VID2 VID3 VID4 VID5 VID6 VID7
12V_FILTER
21
12V_FILTER
D G S IMON 12 11 10 9 8 7 6 5 4 3 2 1 G S 48 D ILIM ROSC VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 PSI BG3 G S D PWM3_SENSE_N PWM3_SENSE_P
VCCP
RFB
CFB 13 IMON 14 VSP 15 16 VSN DIFFOUT COMP VFB VDRP VDFB CSSUM DAC 12VMON NCP5395T 48L 7x7 QFN FLAG = GND
VBST3
TG3 47 SWN3 46 DRVON 45 BST2 44 TG2 43 SWN2 42 12V_FILTER BG2 41 2 1 D G S VCCP 40 SWN1 39 TG1 38 BST1 37 DRVON
RF CH CF
RFB
17 18
RDRP CDFB RDFB RISO RT 12V_FILTER RISO
19 20
12V_FILTER
R 21 22 23
CS4P CS4N CS3P CS3N CS2P CS2N CS1P CS1N EN VR_RDY G4 BG1
24 VCC
25 26 27 28 29 30 31 32 33 34 35 36
C17
D G S G
D
PWM1_SENSE_N PWM1_SENSE_P
+5.0V VTT PWM1_SENSE_P PWM1_SENSE_N
S
VCCP
ENABLE PWM3_SENSE_P PWM3_SENSE_N
Figure 2. Typical 2 Phase Application
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NCP5395T
VTT
R236 PSI#_CPU VID0 VID1 VID2 VID3 VID4 VID5 VID6 VID7 12V_FILTER 21 12V_FILTER D G S D G S 12 11 10 9 8 7 6 5 4 3 2 1 G S D
PWM3_SENSE_N PWM3_SENSE_P
VCCP CFB
ILIM ROSC VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 PSI BG3
12V_FILTER 48 47 46 45 44 43 42 41 12V_FILTER 40 39 38 37 G S C37 VCCP D D G S S PWM1_SENSE_N PWM1_SENSE_P 2 1 D G S D G S D PWM2_SENSE_N PWM2_SENSE_P DRVON 2 1 D G S
RFB
13 IMON 14 VSP 15 VSN
VBST3 TG3 SWN3
RF CH CF
RFB
16 DIFFOUT 17 18 COMP VFB VDRP NCP5395T 48L 7x7 QFN FLAG = GND
DRVON BST2 TG2 SWN2 BG2 VCCP SWN1 TG1 BST1
RDRP 19 CDFB RDFB RT RISO RISO 12V_FILTER
20 VDFB R 21 CSSUM 22 DAC
12V_FILTER
23 12VMON 24 VCC
+5.0V VTT PWM1_SENSE_P PWM1_SENSE_N PWM2_SENSE_P ENABLE PWM2_SENSE_N PWM3_SENSE_P PWM3_SENSE_N 12V_FILTER G
25 26 27 28 29 30 31 32 33 34 35 36
CS4P CS4N CS3P CS3N CS2P CS2N CS1P CS1N EN VR_RDY G4 BG1
Figure 3. Typical 3 Phase Application http://onsemi.com
4
NCP5395T
VTT
PSI#_CPU VID0 VID1 VID2 VID3 VID4 VID5 VID6 VID7
12V_FILTER
21
12V_FILTER D G S D G S G S D PWM3_SENSE_N PWM3_SENSE_P
IMON ILIM ROSC VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 PSI BG3 VCCP 12 11 10 9 8 7 6 5 4 3 2 1
12V_FILTER 48 47 46 45 DRVON 2 1 D G S
RFB CFB RFB RF CF CH
13 IMON 14 VSP 15 16 17 18 VSN
VBST3 TG3 SWN3
DIFFOUT COMP VFB VDRP VDFB CSSUM DAC NCP5395T 48L 7x7 QFN FLAG = GND
DRVON
BST2 44 43 TG2 SWN2 BG2 VCCP SWN1 TG1 42 41 12V_FILTER 40 39 38 37 2 1 G
D G S
D S
RDRP 19 CDFB RDFB RT RISO RISO 12V_FILTER 20 21 22
PWM2_SENSE_N PWM2_SENSE_P
12V_FILTER
CS4P CS4N CS3P CS3N CS2P CS2N CS1P CS1N EN VR_RDY G4 BG1
23 12VMON VCC 24
BST1
D G S VCCP
25 26 27 28 29 30 31 32 33 34 35 36
+5.0V VTT PWM4_GATE PWM1_SENSE_P PWM1_SENSE_N 12V_FILTER PWM2_SENSE_P 21 PWM2_SENSE_N PWM3_SENSE_P PWM3_SENSE_N DRVON PWM4_GATE PWM4_SENSE_P PWM4_SENSE_N G
D G S
D S
PWM1_SENSE_N PWM1_SENSE_P
12V_FILTER
ENABLE
D VCC BST 4 1 DRH 8 OD 7 SW 3 IN 5 DRL 2 PGND 6 NCP5359 G S
D G S G
D PWM4_SENSE_N S PWM4_SENSE_P
Figure 4. Typical 4 Phase Application
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NCP5395T
Table 1. Pin Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 FLAG PSI VID0 VID1 VID2 VID3 VID4 VID5 VID6 VID7/AMD ROSC ILIM IMON VSP VSN DIFFOUT COMP VFB VDRP VDFB CSSUM DAC 12VMON VCC CS4P CS4N CS3P CS3N CS2P CS2N CS1P CS1N EN VR_RDY G4 BG1 BST1 TG1 SWN1 VCCP BG2 SWN2 TG2 BST2 DRVON SWN3 TG3 BST3 GND Symbol BG3 Low side gate drive #3 Power Saving Control. Low = single phase operation; High = normal operation Voltage ID DAC input Voltage ID DAC input Voltage ID DAC input Voltage ID DAC input Voltage ID DAC input Voltage ID DAC input Voltage ID DAC input Voltage ID DAC input. Pull to VCC (5 V) to enable AMD 6-bit DAC code. A resistance from this pin to ground programs the oscillator frequency and provides a 2 V reference for programming the ILIM voltage. Over current shutdown threshold setting. ILIM = VDRP - 1.3 V. Resistor divide ROSC to set threshold 0 to 1.1 V analog signal proportional to the output load current. VSN referenced Clamped to 1.1 Vmax Non-inverting input to the internal differential remote sense amplifier Inverting input to the internal differential remote sense amplifier Output of the differential remote sense amplifier Output of the compensation amplifier Compensation amplifier voltage feedback Voltage output signal proportional to current used for current limit and output voltage droop Droop Amplifier Voltage Feedback Inverted Sum of the Differential Current Sense inputs DAC output used to provide feed forward for dynamic VID Monitor a 12 V input through a resistor divider Power for the internal control circuits with UVLO monitor Non-inverting input to current sense amplifier #4 Inverting input to current sense amplifier #4 Non-inverting input to current sense amplifier #3 Inverting input to current sense amplifier #3 Non-inverting input to current sense amplifier #2 Inverting input to current sense amplifier #2 Non-inverting input to current sense amplifier #1 Inverting input to current sense amplifier #1 Threshold sensitive input. High = startup, Low =shutdown. Open collector output. High indicates that the output is regulating PWM output pulse to gate driver. Low side gate drive #1 Upper MOSFET floating bootstrap supply for driver#1 High side gate drive #1 Switch Node #1 Power VCC for gate drivers with UVLO monitor Low side gate drive #2 Switch Node #2 High side gate drive #2 Upper MOSFET floating bootstrap supply for driver#2 Bidirectional Gate Drive Enable Switch Node #3 High side gate drive #3 Upper MOSFET floating bootstrap supply for driver#3 Power supply return (QFN Flag) Description
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NCP5395T
ABSOLUTE MAXIMUM RATINGS
Rating ELECTRICAL INFORMATION Controller Power Supply Voltages to GND Driver Power Supply Voltages to GND High-Side Gate Driver Supplies: BSTx to SWNx VCC VCCP VBST - VSWN -0.3, 7 -0.3, 15 35 V wrt/GND 40 V 50 ns wrt/GND -0.3, 15 wrt/SWN BOOT + 0.3 V 35 V 50 ns wrt/GND -0.3, 15 wrt/SWN -5 V (200 ns) 35 40 V 50 ns wrt/GND -5 VDC -10 V (200 ns) VCC + 0.3 V -5 V (200 ns) -0.3, 6 0 GND 300 VIMON 1.1 -0.3, 5.5 V V V Symbol Value Unit
High-Side FET Gate Driver Voltages: TGx to SWNx
VTG - VSWN
V
Switch Node: SWNx
VSWN
V
Low-Side Gate Drive: BGx Logic Inputs GND V- Imon Out All Other Pins THERMAL INFORMATION Thermal Characteristic QFN Package (Note 1) Operating Junction Temperature Range (Note 2) Operating Ambient Temperature Range Maximum Storage Temperature Range Moisture Sensitivity Level QFN Package
VBG - AGND VLOGIC VGND
V V V mV V V
RqJA TJ TAMB TSTG MSL
30.5 0 to 125 0 to +70 -55 to +150 1
C/W C C C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. *All signals referenced to GND unless noted otherwise. *The maximum package power dissipation must be observed. 1. JESD 51-5 (1S2P Direct-Attach Method) with 0 LFM 2. Operation at -40C to 0C guaranteed by design, not production tested.
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NCP5395T
ELECTRICAL CHARACTERISTICS
0C < TA < 70C; 0C < TJ < 125C; 4.75 < VCC < 5.25 V; All DAC Codes; CVCC = 0.1 mF unless otherwise noted. Parameter ERROR AMPLIFIER Open Loop DC Gain Open Loop Unity Gain Bandwidth Open Loop Phase Margin Slew Rate CL = 60 pF to GND, RL = 10 kW to GND CL = 60 pF to GND, RL = 10 kW to GND CL = 60 pF to GND, RL = 10 kW to GND DVin = 100 mV, G = -10V/V, DVout = 1.5 V - 2.5 V, CL = 60 pF to GND, DC Load = 125 mA to GND 10 mV of Overdrive, ISOURCE = 2.0 mA 10 mV of Overdrive, ISINK = 500 mA 10 mV of Overdrive, Vout = 3.5 V 10 mV of Overdrive, Vout = 0.1 V DRVON = low DRVON = high DRVON = low DRVON = high - - - - 100 18 70 10 - - - - dB MHz V/ms Test Conditions Min Typ Max Unit
Maximum Output Voltage Minimum Output Voltage Output Source Current Output Sink Current DIFFERENTIAL SUMMING AMPLIFIER V+ Input Pull down Resistance V+ Input Bias Voltage Input Voltage Range (Note 3) -3 dB Bandwidth Closed Loop DC gain VS to Diffout Maximum Output Voltage Minimum Output Voltage Output Source Current Output Sink Current INTERNAL OFFSET VOLTAGE Offset Voltage to the (+) Pin of the Error Amp & the VDRP Pin 3. Design guaranteed.
3.0 - 1.5 0.65
- - 2.0 1.0
- 75 - -
V mV mA mA
- - - 0.8 -0.3
0.6 6.0 0.05 0.88 - 15 1.0 - - 2.0 1.5
- - 0.1 0.95 3.0 - 1.02 - 0.5 - -
kW V V MHz V/V V V mA mA
CL = 80 pF to GND, RL = 10 kW to GND VS+ to VS- = 0.5 V to 1.6 V 10 mV of Overdrive, ISOURCE = 2 mA 10 mV of Overdrive, ISINK = 1 mA 10 mV of Overdrive, Vout = 3 V 10 mV of Overdrive, Vout = 0.2 V
- 0.98 3.0 - 1.5 1.0
-2
0
+2
mV
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NCP5395T
ELECTRICAL CHARACTERISTICS
0C < TA < 70C; 0C < TJ < 125C; 4.75 < VCC < 5.25 V; All DAC Codes; CVCC = 0.1 mF unless otherwise noted. Parameter VDROOP AMPLIFIER Inverting Voltage Range Open Loop DC Gain Open Loop Unity Gain Bandwidth Open Loop Phase Margin Slew Rate Maximum Output Voltage Minimum Output Voltage Output Source Current Output Sink Current CSSUM AMPLIFIER Current Sense Input to VDRP -3 dB Bandwidth Current Summing Amp Output Offset Voltage Maximum CSSUM Output Voltage Minimum CSSUM Output Voltage Output Source Current Output Sink Current PSI Enable High Input Leakage Current Threshold Delay DRVON Output High Voltage Output Low Voltage Delay Time Rise Time Fall Time Internal Pull-Down Resistance VCC Voltage when DRVON Output Valid CURRENT SENSE AMPLIFIERS Input Bias Current Common Mode Input Voltage Range Differential Mode Input Voltage Range Current Sharing Offset CS1 to CSx (Note 3) all VIOS CSx = CSxN = 1.4 V -50 -0.3 -120 -2.5 - - - - 50 2.0 120 2.5 nA V mV mV Sourcing 500 mA Sinking 500 mA Propagation delays CL (PCB) = 20 pF, DVo = 10% to 90% CL (PCB) = 20 pF, DVo = 10% to 90% 3.0 - - - - 35 - - - 10 10 10 70 - - 0.7 - - - 140 2.0 V V ns ns ns kW V External 1k Pull-up to 3.3 V - 450 - - 600 100 1.0 770 - mA mV ns CL = 10 pF to GND, RL = 10 kW to GND CSx - CSNx = 0, CSx = 1.1 V CSx - CSxN = -0.2 V (all phases) ISOURCE = 1 mA CSx - CSxN = 0.7 V (all phases) ISINK = 1 mA Vout = 3.0 V Vout = 0.3 V - -13 3.0 - 1.0 4.0 12 - - - - - - 8.0 - 0.3 - - MHz mV V V mA mA CL = 20 pF to GND including ESD RL = 1 kW to GND CL = 20 pF to GND including ESD RL = 1 kW to GND CL = 20 pF to GND including ESD RL = 1 kW to GND CL = 20 pF to GND including ESD RL = 1 kW to GND 10 mV of Overdrive, ISOURCE = 4.0 mA 10 mV of Overdrive, ISINK = 1.0 mA 10 mV of Overdrive, Vout = 3.0 V 10 mV of Overdrive, Vout = 1.0 V 0 - - - - 3.0 - 4.0 1.0 1.3 100 18 70 10 - - - - 3.0 - - - - - 1.0 - - V dB MHz V/ms V V mA mA Test Conditions Min Typ Max Unit
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NCP5395T
ELECTRICAL CHARACTERISTICS
0C < TA < 70C; 0C < TJ < 125C; 4.75 < VCC < 5.25 V; All DAC Codes; CVCC = 0.1 mF unless otherwise noted. Parameter CURRENT SENSE AMPLIFIERS Current Sense Input to PWM Gain Current Sense Input to CSSUM Gain IMON VDRP to IMON Gain Current Sense Input to VDRP -3 dB Bandwidth Output Referred Offset Voltage Minimum Output Voltage Maximum Output Voltage Output Sink Current Maximum Clamp Voltage OSCILLATOR Switching Frequency Range Switching Frequency Accuracy Switching Frequency Accuracy Switching Frequency Accuracy (2ph or 4ph) Switching Frequency Accuracy (3ph) ROSC Output Voltage MODULATORS (PWM Comparators) Minimum Pulse Width Magnitude of the PWM Ramp 0% Duty Cycle 100% Duty Cycle PWM Phase Angle Error VR_RDY (Power Good) OUTPUT VR_RDY Output Saturation Voltage VR_RDY Rise Time (Note 3) VR_RDY Output Voltage at Power-up IPGD = 10 mA External pull-up of 1 KW to 1.25 V, CTOT = 45 pF, DVo = 10% to 90% VR_RDY pulled up to 5 V via 2 kW, tR(VCC) 3 x tR(5V) 100 ms tR(VCC) 20 ms VR_RDY = 5.5 V via 1 K VCore Increasing, DAC = 1.3 V - - - - 100 - 0.4 150 1.0 V ns V COMP Voltage when the PWM Outputs Remain LO COMP Voltage when the PWM Outputs Remain HI Between Adjacent Phases Fsw = 800 kHz - - 50 1.1 -15 30 1.1 250 1.35 - - - 400 1.6 15 ns V mV V 200 kHz < FSW < 600 kHz 100 kHz < FSW < 1 MHz ROSC = 16.2k ROSC = 16.2k 100 - - 454 468 1.93 - - - - - 2.00 1100 5.0 10 502 518 2.05 kHz % % kHz kHz V 1.325 V > VDRP > 1.75 V CL = 30 pF to GND, RL = 100 kW to GND VDRP = 1.5 V, ISOURCE = 0 mA VDRP = 1.3 V, ISINK = 25 mA Iout = 300 mA Vout = 0.3 V IMON - VSN VDRP = HIGH RLOAD = Open 1.965 - 0 - 1.0 175 1.1 - 4.0 25 - - - - 2.02 - 50 0.1 - - 1.2 V/V MHz mV V V mA V 0 V < CSx - CSxN < 0.1 V, 0 V < CSx - CSxN < 0.1 V 5.45 -3.834 5.75 -3.7 6.05 -3.574 V/V V/V Test Conditions Min Typ Max Unit
VR_RDY High - Output Leakage Current VR_RDY Upper Threshold Voltage (INTEL)
- -
- 300
0.1 250
mA mV (below DAC) mV (below DAC) mV (below DAC) mV (below DAC)
VR_RDY Lower Threshold Voltage (INTEL)
VCore Decreasing, DAC = 1.3 V
390
350
300
VR_RDY Upper Threshold Voltage (AMD)
VCore Increasing, DAC = 1.3 V
-
-
142
VR_RDY Lower Threshold Voltage (AMD)
VCore Decreasing, DAC = 1.3 V
282
-
192
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NCP5395T
ELECTRICAL CHARACTERISTICS
0C < TA < 70C; 0C < TJ < 125C; 4.75 < VCC < 5.25 V; All DAC Codes; CVCC = 0.1 mF unless otherwise noted. Parameter VR_RDY (Power Good) OUTPUT VR_RDY Rising Delay VR_RDY Falling Delay PWM G4 OUTPUT Output High Voltage Mid Output Voltage Output Low Voltage Delay + Rise Time (Note 3) Delay + Fall Time (Note 3) Tri-State Output Leakage (Note 3) Output Impedance - HI or LO State Minimum VCC for Valid PWM Output Level PWM 4 2/3/4 Phase Detection 2 Phase Mode 4 Phase Mode 3 Phase Mode DIGITAL SOFT-START Soft-Start Ramp Time VR11 Vboot time VID7/VR11/AMD/LEGACY INPUT VID Threshold VR11 Input Bias Current Delay Before Latching VID Change (VID Deskewing) (Note 3) AMD Upper Threshold Measured from the Edge of the 1st VID Change Note: When above this threshold the controller will ramp directly to VID without stopping at Vboot 450 -100 200 - 600 - - - 770 100 300 4.8 mV nA ns V DAC = 0 to DAC = 1.1 V Not used in Legacy Startup 1.0 400 - 500 1.3 600 ms ms Note Gate 4 tied to VCC Note Gate Driver will pull to 1.5 V Note Gate 4 tied to GND 3.2 1.2 0 - - - VCC 2.8 0.8 V V V Sinking 500 mA CL (PCB) = 50 pF, DVo = VCC to GND CL (PCB) = 50 pF, DVo = GND to VCC Gx = 2.5 V, x = 1-4 Max Resistance to VCC (HI) or GND (LO) Sourcing 500 mA 3.0 1.4 - - - - - - - 1.5 - 10 10 - 75 - - 1.6 0.7 - - 1.5 150 2.0 V V V ns ns mA W V VCore Increasing VCore Decreasing - - 250 5.0 - - ms ms Test Conditions Min Typ Max Unit
AMD Lower Threshold
3.33
-
-
V
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NCP5395T
ELECTRICAL CHARACTERISTICS
0C < TA < 70C; 0C < TJ < 125C; 4.75 < VCC < 5.25 V; All DAC Codes; CVCC = 0.1 mF unless otherwise noted. Parameter ENABLE INPUT Enable High Input Leakage Current VR11.1 Threshold AMD Upper Threshold AMD Lower Threshold AMD Total Hysteresis Enable Delay Time CURRENT LIMIT ILIM to VDRP Gain ILIM to VRDP Gain in PSI 4 Phase ILIM to VDRP Gain in PSI 3 Phase ILIM to VDRP Gain in PSI 2 Phase ILIM Pin Input Bias Current ILIM Pin Working Voltage Range ILIM accuracy Delay OVERVOLTAGE PROTECTION VR11 Over Voltage Threshold AMD Over Voltage Threshold Delay UNDERVOLTAGE PROTECTION VCC UVLO Start Threshold VCC UVLO Stop Threshold VCC UVLO Hysteresis 12VMON UVLO 12VMON (High Threshold) 12VMON (Low Threshold) DAC OUTPUT Output Source Current Output Sink Current VID INPUTS Threshold VR11 Mode Leakage AMD Mode Input Bias Current Delay before Latching VID Change (VID Deskewing) (Note 3) Measured from the edge of the VID change 1st 450 -100 10 200 600 - - - 770 100 25 300 mV nA mA ns Vout = 1.6 V Vout = 0.3 V 0 5.0 - - 5.0 16 mA mA VCC Valid VCC Valid - 0.4 0.6 0.5 0.8 - v v 4.0 3.8 150 4.25 4.05 200 4.5 4.3 - V V mV DAC+ 160 DAC+ 210 - DAC+ 190 DAC+ 235 - DAC+ 210 DAC+ 260 100 mV mV ns Measured with respect to the ILIM setting 0.97 - - - - 0.1 -25 - 1.00 0.25 0.333 0.5 0.1 - - - 1.03 - - - 1.0 2.0 25 120 V/V V/V V/V V/V mA V mV ns Rising- Falling Threshold Measure time from Enable transitioning HI to when SS begins Pull-up to 1.3 V - 450 - 0.9 - - - 600 1.3 1.1 200 3.5 200 770 1.5 - - - nA mV V V mV ms Test Conditions Min Typ Max Unit
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NCP5395T
ELECTRICAL CHARACTERISTICS
0C < TA < 70C; 0C < TJ < 125C; 4.75 < VCC < 5.25 V; All DAC Codes; CVCC = 0.1 mF unless otherwise noted. Parameter DIGITAL DAC SLEW RATE LIMITER Slew Rate Limit (Intel Mode) Slew Rate Limit (AMD Mode) Soft-Start Slew Rate INPUT SUPPLY CURRENT VCC Operating Current VCCP SUPPLY VOLTAGE VCCP UVLO Start Threshold VCCP UVLO Stop Threshold VCCP UVLO Hysteresis VCCP POR BOOST PIN UVLO BOOST VCC UVLO Start Threshold BOOST VCC UVLO Stop Threshold BOOST VCC UVLO Hysteresis BOOST SUPPLY CURRENT IVCCP_NORM Standby Current IBST1_SD Standby Current IBST2_SD Standby Current IBST3_SD Standby Current Vswx Output Overvoltage Trip Threshold at Startup EN = VCC, VCCP = 12 V IN = VCCP, VCCP = 12 V IN = GND, VCCP = 12 V IN = GND, VCCP = 12 V 1st power on) 1.7 - 2.03 V Power Startup time, VCC > 9 V - - - - - 0.25 0.25 0.25 2.5 2.5 2.5 2.5 mA mA mA mA 3.45 3.3 50 200 4.15 3.85 - V V mV Voltage at which the Driver OVP becomes active 8.2 7.2 1.0 3.0 9.0 8.0 - 3.17 9.5 8.5 - - V V V EN Low, No PWM 20 - 42 mA 12.5 3.125 - - - 0.84 15 3.75 - mV/ms mV/ms mV/ms Test Conditions Min Typ Max Unit
STARTUP HIGH SIDE SHORT TRIP (Active only during
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NCP5395T
ELECTRICAL CHARACTERISTICS
0C < TA < 70C; 0C < TJ < 125C; 4.75 < VCC < 5.25 V; All DAC Codes; CVCC = 0.1 mF unless otherwise noted. Parameter HIGH SIDE DRIVER RH_TG Output Resistance, Sourcing RH_TG Output Resistance, Sinking TrDRVH Transition Time TfDRVH Transition Time TpdhDRVH Propagation Delay (Note 4) LOW SIDE DRIVER RH_BG Output Resistance, Sourcing RL_BG Output Resistance, Sinking TrDRVL Transition Time TfDRVL Transition Time TpdhDRVL Propagation Delay (Note 4) VNCDT Negative Current Detector Threshold (Note 3) THERMAL SHUTDOWN Tsd Thermal Shutdown (Note 3) Tsdhys Thermal Shutdown Hysteresis (Note 3) VRM 11 DAC System Voltage Accuracy 1.0 V < DAC < 1.6 V 0.8 V < DAC < 1.0 V 0.5 V < DAC < 0.8 V - - - - - - 0.5 5.0 8.0 % mV mV 150 - 170 20 - - C C SW = GND SW = VCC CLOAD = 3 nF CLOAD = 3 nF Driving High, CLOAD = 3 nF, VCCP = 12 V - - - - - - 1.6 1.0 20 20 15 -1.0 5.0 2.5 - - - - W W ns ns ns mV VBST - VSW = 12 V VBST - VSW = 12 V CLOAD = 3 nF, VBST - VSW = 12 V CLOAD = 3 nF, VBST - VSW = 12 V Driving High, CLOAD = 3 nF, VCCP = 12 V - - - - - 1.8 1.0 25 20 15 5.0 2.5 - - - ns ns ns W Test Conditions Min Typ Max Unit
4. For propagation delays, "tpdh" refers to the specified signal going high "tpdl" refers to it going low. Reference Gate Timing Diagram.
IN DRVL
tpdlDRVL
tfDRVL 90%
90% 2V 10% tpdhDRVH thDRVH tpdlDRVH tfDRVH 10% trDRVL
90% 10% DRVH-SW
90%
2V
10% tpdhDRVL
SW
Figure 5. Timing Diagram
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NCP5395T
Table 2. VRM11 VID CODES
VID7 800 mV 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID6 400 mV 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID5 200 mV 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID4 100 mV 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID3 50 mV 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 VID2 25 mV 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 VID1 12.5 mV 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID0 6.25 mV 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1.60000 1.59375 1.58750 1.58125 1.57500 1.56875 1.56250 1.55625 1.55000 1.54375 1.53750 1.53125 1.52500 1.51875 1.51250 1.50625 1.50000 1.49375 1.48750 1.48125 1.47500 1.46875 1.46250 1.45625 1.45000 1.44375 1.43750 1.43125 1.42500 1.41875 1.41250 1.40625 1.40000 1.39375 1.38750 1.38125 1.37500 1.36875 1.36250 1.35625 1.35000 1.34375 1.33750 1.33125 Voltage (V) HEX 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D
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NCP5395T
Table 2. VRM11 VID CODES
VID7 800 mV 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID6 400 mV 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID5 200 mV 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID4 100 mV 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 VID3 50 mV 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 VID2 25 mV 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 VID1 12.5 mV 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VID0 6.25 mV 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Voltage (V) 1.32500 1.31875 1.31250 1.30625 1.30000 1.29375 1.28750 1.28125 1.27500 1.26875 1.26250 1.25625 1.25000 1.24375 1.23750 1.23125 1.22500 1.21875 1.21250 1.20625 1.20000 1.19375 1.18750 1.18125 1.17500 1.16875 1.16250 1.15625 1.15000 1.14375 1.13750 1.13125 1.12500 1.11875 1.11250 1.10625 1.10000 1.09375 1.08750 1.08125 1.07500 1.06875 1.06250 1.05625 1.05000 1.04375 HEX 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B
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NCP5395T
Table 2. VRM11 VID CODES
VID7 800 mV 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 VID6 400 mV 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 VID5 200 mV 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 VID4 100 mV 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 VID3 50 mV 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 VID2 25 mV 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 VID1 12.5 mV 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID0 6.25 mV 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Voltage (V) 1.03750 1.03125 1.02500 1.01875 1.01250 1.00625 1.00000 0.99375 0.98750 0.98125 0.97500 0.96875 0.96250 0.95625 0.95000 0.94375 0.93750 0.93125 0.92500 0.91875 0.91250 0.90625 0.90000 0.89375 0.88750 0.88125 0.87500 0.86875 0.86250 0.85625 0.85000 0.84375 0.83750 0.83125 0.82500 0.81875 0.81250 0.80625 0.80000 0.79375 0.78750 0.78125 0.77500 0.76875 0.76250 0.75625 HEX 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F 80 81 82 83 84 85 86 87 88 89
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NCP5395T
Table 2. VRM11 VID CODES
VID7 800 mV 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID6 400 mV 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 VID5 200 mV 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID4 100 mV 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 VID3 50 mV 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 1 1 VID2 25 mV 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 1 1 VID1 12.5 mV 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 VID0 6.25 mV 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 Voltage (V) 0.75000 0.74375 0.73750 0.73125 0.72500 0.71875 0.71250 0.70625 0.70000 0.69375 0.68750 0.68125 0.67500 0.66875 0.66250 0.65625 0.65000 0.64375 0.63750 0.63125 0.62500 0.61875 0.61250 0.60625 0.60000 0.59375 0.58750 0.58125 0.57500 0.56875 0.56250 0.55625 0.55000 0.54375 0.53750 0.53125 0.52500 0.51875 0.51250 0.50625 0.50000 OFF OFF HEX 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 FE FF
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NCP5395T
Parameter AMD DAC System Voltage Accuracy 1.0 V < DAC < 1.55V 0.6 V DAC < 1.0V 0.375 V < DAC < 0.6V - - - - - - 0.5 1.0 -2.0, +3.0 % % % Test Condition MIN TYP MAX Units
5. NOTE: Internal DAC voltage is centered 19 mV below the listed voltage for VR11.1. No DAC offset is implemented for AMD operation. DAC should be equal to the Nominal Vout shown in the table.
Table 3. AMD PROCESSOR 6-BIT VID CODE
(VID) Codes VID5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 VID3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 VID2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 VID1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Nominal Vout 1.550 1.525 1.500 1.475 1.450 1.425 1.400 1.375 1.350 1.325 1.300 1.275 1.250 1.225 1.200 1.175 1.150 1.125 1.100 1.075 1.050 1.025 1.000 0.975 0.950 0.925 0.900 0.875 0.850 0.825 0.800 0.775 0.7625 0.7500 Units V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V
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NCP5395T
Table 3. AMD PROCESSOR 6-BIT VID CODE
(VID) Codes VID5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID3 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 VID2 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Nominal Vout 0.7375 0.7250 0.7125 0.7000 0.6875 0.6750 0.6625 0.6500 0.6375 0.6250 0.6125 0.6000 0.5875 0.5750 0.5625 0.5500 0.5375 0.5250 0.5125 0.5000 0.4875 0.4750 0.4625 0.4500 0.4375 0.4250 0.4125 0.4000 0.3875 0.3750 Units V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V
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NCP5395T
FUNCTIONAL DESCRIPTIONS
General
The NCP5395T dual edge modulated multiphase PWM controller is specifically designed with the necessary features for a high current CPU system. The IC consists of the following blocks: Precision Flexible DAC, Differential Remote Voltage Sense Amplifier, High Performance Voltage Error Amplifier, Differential Current Feedback Amplifiers, Precision Oscillator and Saw-tooth Generator, and PWM Comparators with Hysteresis. The controller also supports power saving mode as per Intel VR11.1 by accurately monitoring the current and switching between multi-phase and single phase operations as requested by the microprocessor system. Protection features include: Undervoltage Lockout, Soft-Start, Overcurrent Protection, Overvoltage Protection, and Power Good Monitor.
Precision Programmable DAC
sums the remote output voltage with a 1.3 V reference. The resulting voltage at the output of the remote sense amplifier is:
V Diffout + V out ) 1.3 V * V dac * V outreturn
This signal then goes through a standard compensation circuit and into the inverting input of the error amplifier. The non-inverting input of the error amplifier is also connected to the 1.3 V reference. The 1.3 V reference then is subtracted out and the error signal at the comp pin of the error amplifier is as normally expected:
V comp + V dac * V out
The non-inverting input of the remote sense amplifier is pulled low through a small current sink during a fault condition to prevent accidental charging of the regulator output.
2/3/4 Phase Operation
A precision flexible DAC is provided. The DAC will conform to 2 different specifications: AMD or VR11.1. The VID7/AMD pin is provided to determine which DAC specification will be used and which soft-start mode the part will use for power up. There are two soft-start modes. If VID7/AMD is above it's threshold the device will soft-start and ramp directly to the DAC code present on the VID inputs. The following truth table describes the functionality:
VID7/AMD Pin Above AMD Threshold Below AMD Threshold VID7 Not active Active Enable Pin Mode AMD Thresholds VR11.1 Thresholds Soft-Start Mode Ramp to VID Ramp to Vboot
The part can be configured to 2-, 3-, or 4-phase mode. In 2- or 3-phase mode, the internal drivers will be used. In 4-phase mode, an external driver must be used to drive phase 4. The NCP5359 driver is suggested to be used with the controller. The input to G4 pin will decide which phase mode the system is in operation. Please refer to the Application Schematics for more information.
High Performance Voltage Error Amplifier
A high performance voltage error amplifier is provided. The error amplifier's inverting input is VFB and its output is COMP. A standard type 3 compensation circuit is used compensate the system. This involves a 3 pole, 2 zero compensation network. The comp pin is pulled to ground before soft-start for smooth start up.
Differential Current Sense
VID Inputs
VID0-VID7 control the target regulation voltage during normal operation. In AMD mode the VID capture is enabled just before soft-start. In VR11 mode the VID capture is enabled at the end of the VBOOT waiting period. If the VID is valid the DAC will track to it. If an invalid VID occurs it will be ignored for 10 ms before the controller shuts down.
Remote Sense Amplifier
A high performance differential amplifier is provided to accurately sense the output voltage of the regulator. The non-inverting input should be connected to the regulator's output voltage. The inverting input should be connected to the return line of the regulator. Both connection points are intended to be at a remote point so that the most accurate reading of the output voltage can be obtained. The amplifier is configured in a very unique way. First, the gain of the amplifier is internally set to unity. Second, both the inverting and non-inverting inputs of the amplifier are summing nodes. The inverting input sums the output voltage return voltage with the DAC voltage. The non-inverting input
Four differential amplifiers are provided to sense the output current of each phase. These current sense amplifiers sense the current through the corresponding phase. A voltage is generated across a current sense element such as an inductor or sense resistor. The sense element should be between 0.3 mW and 1.5 mW. It is possible to sense both negative and positive going current. The information is used to create the signal CSSUM and provide feedback for current sharing.
Precision Oscillator
A programmable precision oscillator is provided. This oscillator is programmed by the summed resistance of an oscillator resistor and a current limit resistor. The output voltage of this pin is 2V used as the reference for the current limit. The oscillator frequency range is 125 KHz/phase to 1000 KHz/phase. The oscillator frequency is proportional to the current drawn out of the OSC pin. Connecting a resistor (Rosc) from OSC pin to the ground will set the target oscillator frequency. The relation between the Rosc and Fsw can be described as below:
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NCP5395T
Rosc = 15530 x Fsw^(-1.111)
PWM Comparators Over Voltage Protection
Four PWM comparators are incorporated within the IC. The non-inverting input of the comparators is connected to the output of the error amplifier. The inverting input is connected to a summed output of the phase current and the oscillator ramp voltage with an offset. The output of the comparator generates the PWM control signals. During steady state operation, the duty cycle will center on the valley of the saw-tooth waveform. During a transient event, the controller will operate somewhat hysteretic, with the duty cycle climbing along either the down ramp, up ramp, or both.
Soft-Start
The output voltage is monitored at the input of the differential amplifier. During normal operation, if the output voltage exceeds the DAC voltage by 185 mV, or 285 mV if in AMD mode, the VR_RDY flag will transition low the high side gate drivers set to low, and the low side gate drivers are all brought to high until the voltage falls below the OVP threshold. If the over voltage trip 8 times the output voltage will shut down. The OVP will not shut down the controller if it occurs during soft-start. This is to allow the controller to pull the output down to the DAC voltage and start up into a pre-charged output. The VCCP power on reset OVP feature is used to protect the CPU during start up. When VCCP is higher than 3.2 V, the gate driver will monitor the switching node SW pin. If SWNx pin higher than 1.9 V, the bottom gate will be forced to high for discharge of the output capacitor. This works best if the 5 volt standby is diode OR'ed into VCCP with the 12 V rail. The fault mode will be latched and the DRVON pin will be forced to low, unless VCCP is reduced below the UVLO threshold.
Power Saving Mode VCCP Power ON Reset OVP
Soft-start is implemented internally. A digital counter steps the DAC up from zero to the target voltage based on the predetermined rate in the spec table. There are 2 possible soft start modes: VR11 and AMD. AMD mode simply ramps Vcore from 0 V directly to the DAC setting. The VR11 mode ramps DAC to 1.1 V, pauses for 500 ms, reads the DAC setting, then ramps to the final DAC setting.
Digital Slew Rate Limiter / Soft-Start Block
The slew rate limiter and the soft-start block are to be implemented with a digital up/down counter controlled by an oscillator that is synchronized to VID line changes. During soft-start the DAC will ramp at the soft-start rate, after soft start is complete the ramp rate will follow either the Intel or the AMD slew rate depending on the mode.
Under Voltage Lockouts
An under voltage circuit senses the VCC input of the controller and the VCCP input of the driver. During power up the input voltage to the controller is monitored. The PWM outputs and the soft start circuit are disabled until the input voltage exceeds the threshold voltage of the comparators. Hysteresis is incorporated within the comparators. The DRVON is held low until VCCP reaches the start threshold during startup. If VCCP decreases below the stop threshold, the output gate will be forced low unit input voltage VCCP rises above the startup threshold.
Over Current Latch
The controller is designed to allow power saving operation to maintain a maximum efficiency. When a low PSI signal from microcontroller is received, the controller will keep one phase operating while shedding other phases. The active one phase will operate in diode emulation mode, minimizing power losses in light load. The device also maintains an RPM operation in power saving mode. The 12VMON input will be used for two purposes: feedforward input supply information for RPM mode and secondary power input voltage UVLO. When the low PSI signal is de-asserted, the dropped phases will be pulled back in to be ready for heavy load and the device will be back to regular PWM mode.
Adaptive Non-overlap
A programmable over current latch is incorporated within the IC. The oscillator pin provides the reference voltage for this pin. A resistor divider from the OSC pin generates the ILIM voltage. The latch is set when the current information on Vdroop exceeds the programmed voltage plus a 1.3 V offset. DRVON is immediately set low. To recover the part must be reset by the EN pin or by cycling VCC.
UVLO Monitor
The non-overlap dead time control is used to avoid shoot through damage to the power MOSFETs. When the PWM signal pull high, DRVL will go low after a propagation delay, the controller monitors the switching node (SWN) pin voltage and the gate voltage of the MOSFET to know the status of the MOSFET. When the low side MOSFET status is off an internal timer will delay turn on of the high-side MOSFET. When the PWM pull low, gate DRVH will go low after the propagation delay (tpdDRVH). The time to turn off the high side MOSFET is depending on the total gate charge of the high-side MOSFET. A timer will be triggered once the high side MOSFET is turn off to delay the turn on the low-side MOSFET.
Layout Guidelines
If the output voltage falls greater than 300 mV below the DAC voltage for more than 5 ms the UVLO comparator will trip sending the VR_RDY signal low.
Layout is very important thing for design a DC-DC converter. Bootstrap capacitor and Vin capacitor are most
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NCP5395T
critical items, it should be placed as close as to the controller IC. Another item is using a GND plane. Ground plane can provide a good return path for gate drives for reducing the ground noise. Therefore GND pin should be directly connected to the ground plane and close to the low-side
1.25 V
MOSFET source pin. Also, the gate drive trace should be considered. The gate drives has a high di/dt when switching, therefore a minimized gate drives trace can reduce the di/dv, raise and fall time for reduce the switching loss.
ENABLE 1.25 V VID Not Valid 1 ms - 20 ms Rise Time
VID Captured
VID Valid
5V
12 V
12 V 1 ms - 20 ms Rise Time 5 and 12 Good VR11 Soft-start Mode Latched
DRVON
3.5 ms Calibration Time Soft-start Slew Rate DAC Setting
1.10 V Soft-start Slew Rate 500 ms VOUT/DAC
500 ms
VR_RDY
Figure 6. VR11.1 Start Up Timing Diagram
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NCP5395T
ENABLE 5V VID7/AMD
1 ms - 20 ms Rise Time
5V
VCC
1 ms - 20 ms Rise Time
12 V
9.5 V
VCCP
VCC and VCCP UVLO
AMD/Legacy Soft Start Mode Latched
3.5 ms Calibration Time
DRVON DAC Setting SS Slew Rate
VOUT/DAC 500 ms VR_RDY
Figure 7. AMD / Legacy Start Up Timing Diagram
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NCP5395T
PACKAGE DIMENSIONS
QFN48, 7x7, 0.5P CASE 485AJ-01 ISSUE O
D
PIN 1 LOCATION
AB
NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO THE PLATED TERMINAL AND IS MEASURED ABETWEEN 0.15 AND 0.30 MM FROM TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. DIM A A1 A3 b D D2 E E2 e K L MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.20 0.30 7.00 BSC 5.00 5.20 7.00 BSC 5.00 5.20 0.50 BSC 0.20 --- 0.30 0.50
2X
0.15 C
2X DETAIL A OPTIONAL CONSTRUCTION 2X SCALE
0.15 C 0.05 C 0.08 C
NOTE 4
DETAIL A 13 12
1 48 48X 37
L
The products described herein (NCP5395T), may be covered by one or more of the following U.S. patents; US07057381.There may be other patents pending. Devices are ESD sensitive, handling precaution recommended.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative
EE EE EE
TOP VIEW (A3) A1 SIDE VIEW D2
25
E L
A
SOLDERING FOOTPRINT*
C
SEATING PLANE
5.20 1
2X
K
2X
7.30
E2
0.63
48X
36
0.30 b 0.10 C A B 0.05 C
NOTE 3
48X
0.50 PITCH
DIMENSIONS: MILLIMETERS
e e/2 BOTTOM VIEW
48X
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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NCP5395T/D

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